|
|
IC流程 |
Cadence |
Synopsys |
Mentor |
other |
|
模拟设计 |
系统集成设计环境 |
IC618/ICADV |
IDQ/icvalidator |
catapilt |
Xilinx vivado(ise) quartusprimepro (altera) ADS(keysight) |
|
|
模拟与版图 |
virtuoso schematic virtuoso layout |
laker_ADP |
|
|
|
|
物理验证 |
PVS |
ICV |
Calibre |
|
|
|
寄生参数提取 |
Quantus |
Star-RCXT |
Calibre-XACT |
|
|
|
k库 |
Liberate |
Silicon-smart |
|
|
|
数字设计 |
Verilog RTL代码 |
|
|
|
Visual Studio Code、Sublime Text、Vim |
|
|
波形，仿真调试(DBUG) |
verisium INDAGOMAIN |
Verdi(novas) custom_waveview |
|
|
|
|
IP配置生成 |
|
coretools/LC |
|
socrate (ARM) |
|
|
RTL仿真 |
xcelium(incisive) Verilog-XL NC Verilog |
VCS |
ModelSim支持windows适合入门 questasim |
|
|
|
形式验证(formal verification) |
Jasper/pegasus |
VC FORMAL(FM) |
guesta formal |
|
|
|
逻辑等效验证(logic equivalenceverification) |
conformal |
formailty |
veloce |
|
|
|
设计约束和CDC检查(constraintsand CDC checking) |
conformal |
spypglass |
quest CDC |
|
|
|
低功耗设计 |
Conformal |
VC-LP |
|
|
|
|
验证平台 |
VIPCAT |
VlP/testsuit |
AVERY |
|
|
|
综合 |
Genus |
DC(desing compile) |
|
|
|
|
静态时序分析(STA) |
genus |
design compile |
|
XTOP(九天) |
|
|
Spice仿真 |
Spectre |
Hspice primesim/XA |
QuestaSim |
华大九天 alps |
|
|
时序验证 |
Tempus |
Primetime SpyGlass |
|
|
|
|
可测试性设计(DFT) |
modus |
DFT Compiler testmax |
Tessent |
|
|
|
布局布线 |
innovus/DDl |
IC COMILER l/fusion compiler/SYN |
tanner |
SKIPER(九天) |
|
|
FPGA IDE |
|
|
|
Xilinx vivado(ise) QuartusII design |
|
|
功耗优化与分析 |
Voltus （ssv） joules |
primepower |
|
Ansys Redhawk |
|
|
IR DROP/EM分析 |
voltus/SlG |
|
|
redhawk/seascape,ansys)，Patron(九天) |
|
|
SPB设计 |
OrCad Allegro |
|
|
|
|
|
寄存器参数提取(parasiticextraction) |
quantus/qrc |
starRC |
calibre/DRC/LVS/ XRC |
RCExplorer(九天) |
|
|
物理验证(PHYsical verification) |
pegasus/ASSURAPVS |
IC validator |
calibre |
Argus (九天) |
|
|
其他(memory compiler) |
vmanager |
Custom Compiler lib_compiler |
|
MC2(TSMC).ARTISAN(arm) vscode,matlab |
IC流程常用的工具汇总-更新20240612